The present invention relates to a semiconductor device, and more particularly, to a semiconductor device which has pads formed on the surface thereof for electric communications to the outside. The present invention also relates to a method of manufacturing the semiconductor device.
The primary importance to the development of large capacity semiconductor devices includes a lower cost and faster operations of the devices through a reduction in chip sizes. Further, in semiconductor devices intended for providing higher performance and more functions, bonding pads (hereinafter simply called the “pads”) for electrical connections of a chip to the outside must be formed at a narrower pitch in order to simultaneously increase the number of input/output terminals and reduce the chip size. When 240 pads are formed, for example, along four sides of a chip in the shape of a 5-mm square, each pad must be reduced in width to 70 micrometers or less when the pads are arranged at intervals of 10 micrometers.
On the other hand, due to a reduction in the pad size and an associated reduction in a bonding diameter of a bonding wire (hereinafter simply called the “wire”) bonded to a pad, resulting in a localized dynamic load with which a wire is pressed onto a pad, a wire can be bonded to a pad insufficiently depending on bonding conditions, making the wire more prone to falling off, the pad can peel off its underlying insulating layer on the interface therebetween, and a cleavage can run deep into the interior of the semiconductor chip.
To address the foregoing problems, pad structures disclosed in JP-A-2000-269265 and JP-A-2000-114309 comprise a layer made of tungsten or the like having plugs below a pad layer for increasing a bonding strength between the pad layer and wires.